Memory plays an indispensable role in computer industries. Usually, a traditional memory is classified into a dynamic random access memory (DRAM) or a static random access memory (SRAM) according to its data storage capability. DRAM is advantageous for its small size, but requires periodic refresh to prevent data loss due to current leakage. SRAM is advantageous for its simple operations, but occupies a large chip area.
In order to combine the advantages of both DRAM and SRAM, a pseudo SRAM consisted of a DRAM macro core with a traditional SRAM interface has been proposed. In the pseudo SRAM, an on-chip refresh circuit that frees the user from the need to take care of refresh task. Compared with traditional CMOS SRAM, pseudo SRAM has advantage in higher density, higher speed, smaller die size and DRAM compatible process.
Nowadays, various types of hidden refresh methods for pseudo SRAM have been proposed and also have respective advantages and disadvantages. Therefore, there still is a need to provide a new refresh strategy for pseudo SRAM.